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Well, I guess that would depend on the throughput of the whole system. If 480 ARM processors are only as fast as a handful of x86 cores, your memory bandwidth should prove no more a bottleneck. The article is sadly lacking on details such as clock speed, etc.
The nice thing about it is that it would offer a great deal of flexibility depending on how parallelizable your code is. Nobody's claiming you have to use all 480 cores at the same time; you could turn off half or more of them if that's all you can use, if your memory bus proves inadequate for your current task.
As always, the question is how many SMP (if any) separate nodes will be used to construct this beast and which type of interconnect will be used to connect the different nodes.
480 cores might seem cool, but if its composed of 120 quad core nodes with a slow 1GbE interconnect, this machine will be limited to niche markets.
- Gilboa



