Linked by Thom Holwerda on Sun 16th Apr 2006 15:36 UTC
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Member since:
2005-11-16
I think the above could be achieved with a solution called 'memory map'. Just like a process has a page map, a software component should also have a memory map, i.e. a range of addresses that it is allowed to access.
Accessing RAM is slow, but accessing several levels of the paging structures and severel levels of "memory map" structures and the final physical RAM location (every time the CPU accesses RAM) would be unbearable. That's why CPUs cache the paging structures (TLB), and that's why they'd need to cache the "memory map structures". If you're going to change the "memory map" structures every time the CPU changes between software components then you'll lose the benefits of this caching and end up with "memory map structure cache" misses.
You might aswell just change the paging structures instead (which is what micro-kernels do)...