Linked by Thom Holwerda on Thu 7th Jul 2005 19:16 UTC
IBM IBM has today presented various new versions of their G5 processor at the Power Everywhere Forum in Japan. Firstly, it introduced the much-anticipated PowerPC 970MP, the dual-core version of the G5. In addition, they also announced 3 low-power G5s, ranging from 1.2Ghz at 13W to 1.6Ghz at 16W. These processors will most likely find their way into Apple's Macs.
Permalink for comment 1516
To read all comments associated with this story, please click here.
RE: p m
by rayiner on Fri 8th Jul 2005 20:38 UTC in reply to "p m"
rayiner
Member since:
2005-07-06

so what is it? right it is the 2mbyte l2 cache.

Yep, the 2MB of very low latency L2 cache.

the itanium 2 is not boundet to 32 bit fixed lenght instructions.

Itanium's instruction format is even more cumbersome and cache-hostile than a RISC's!

i don't say ppc is a slow architekture, i like ppc, but its time to extend the architekture with direct 64 bit instruction (like i said at #76 i don't know if the instruction groups of the power4/ppc970 slow the processors down, but i think they will be faster with direct 64 bit instruction loading.

I don't think you really understand the concept of a 64-bit instruction. 64-bit instructions are 64-bit because they operate on 64-bit operands, not because they are 64-bits in length. Generally, the only constraints 32-bit instructions pose for 64-bit code is the inability to load 64-bit immediates with a single instruction. Generally, code doesn't do this nearly enough for it to be a significant bottleneck.

Reply Parent Score: 1