Linked by Thom Holwerda on Mon 20th Aug 2007 19:20 UTC
"A new startup out of MIT emerged from stealth mode today to announce that they're shipping a 64-core processor for the embedded market. The company, called Tilera, was founded by Dr. Anat Agarwal, the MIT professor behind the famous and venerable Raw project on which Tilera's first product, the TILE64 processor, is based. Tilera's director of marketing, Bob Dowd, told Ars that TILE64 represents a "sea change in the computing industry", and the company's CEO isn't shy about pitching the chip as the "first significant new chip architectural development in a decade". So let's take an initial look at what was announced about TILE64 today, with further information to follow as it becomes available."
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Member since:
2005-07-06
The Core 2 is actually less RISC-y internally than the P4. The P4 is internally a pure u-op design. The Core 2 caries fused u-ops (eg: mem-op instructions) through much of the frontend of the core.
As for PPC, ARM, and MIPS, one of those three does not belong. MIPS is a great instruction set. PowerPC is poo.