Linked by Thom Holwerda on Mon 16th Jun 2008 21:51 UTC, submitted by irbis
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Member since:
2005-11-10
Riiiiiiiight,
Here on planet earth, under similar conditions (same ISA, system, OS, configuration and optimization flags) there is no way a wider CPU, with better OOO scheduler, more aggressive branch predictor, larger caches, and which is running almost 25% faster clock cycle performs wors.
Unless AMD has some sort of pixie dust which breaks the rules of physics, or you are simply making stuff up.
I have both quad Opterons and Core2 Quads extensively, clock by clock the Core2 quad xeons take the Barcelona Opterons to the woodshed. Only in some very rare FPU codes the Opteron can use the memory controller to better stream data as opposed to the Quad Xeon. But if compare a 3Ghz Quad Xeon to a 2.2Ghz Quad Barcelona, I am yet to see a single piece of code I use that the Xeon is slower, the Barcelona for the most part is embarrassingly slower than the Xeon.
AMD is going to have to pull many hat tricks to overcome the fact that a) It does not have a fresh microarchitecture to compete with Nehalem (which is an almost completely new microarch from Intel), b) It can barely manage to produce 65nm parts, never mind that intel has had 45nm online for a while, with 3*nm nodes almost ready to go.
So indeed AMD will need all the pixie dust and denial to overcome the fact that they are at least their microarchitecture is 1 generation behind and unless they manage to pull it off and skip 45nm altogether, their fab may be 2 generations behind.
With the amount of money they are hemorrhaging, I have no clue where they are going to raise the hundreds of millions it takes to design a new microarchitecture and the billions it takes to get the new fab lines ready for sub 65nm nodes.