OSNews

Counting the number of different instructions on a CPU is not so easy as it sounds. For example:

CPU A has an ADD instruction, and ADC (add with carry) instruction, ADDI and ADCI (immediate versions of the above) and several shift/rotate instructions.

CPU B has a single ADD instruction with a modification bit that specifies whether the carry flag is used and a bit that specifies if the next 12 bits is read as an immediate constant or as a register that can optionally be shifted or rotated.

So which CPU has more instruction? You could choose to read every combination of bits that do not specify registers or constants as separate instructions or treat all the combinations as a single parameterised instruction. So you very quickly end up comparing apples to oranges when you try to count instructions.

RISC is usually read as meaning "reduced complexity instruction set". This often implied lower cycle count per instructions, but it was not lowering cycle count that was the main motivation, it was providing the most performance given a limited transistor budget. In comparison, 80386 (1985) used 275000 transistors while ARM1 (1985) used 24000 transistors and ARM2 (1987) used 25000 transistors. Granted, the 80386 had address translation on chip, but so did the later ARM600 which used 33500 transistors.

In any case, given the transistor budgets these days, the RISC vs. CISC distinction is getting increasingly muddied, and the challenge these days is not so much getting the most performance for a given transistor budget (as transistors are cheap), but rather for a given power budget. These are not entirely unrelated, though.