Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
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by Alfman on Fri 20th May 2011 16:25 UTC
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I am concerned that you are still claiming that running threads is more scalable than a non-threaded approach. It is false. More flexible, yes, more scalable (or better performing), no.

As per usual, I'll note that threads are best suited for CPU bound tasks with relatively rare synchronization. Popup/Micro-threads doing trivial tasks are typically short-lived with high overhead.

Thread creation and accounting cost can be reduced to the bare minimum, but synchronization primitives will always be an inherent bottleneck since they cannot operate at CPU speeds and must be serialized over the bus. As the number of micro-threads increases, the bus itself becomes a point of contention and thus the entire system looses performance.

Again, I'll refer to the asynchronous model as having solved these problems. By handling events asynchronously without threads, all of the overhead disappears since no blocking/synchronization is necessary. Since only one stack is needed for CPU, it should fit entirely within the CPU's L1 cache.

Tasks can even consume many more CPU cycles and still beat the micro-threaded model.

This doesn't even get into the prevalence of multi-threaded bugs and the difficulty in debugging them.

If a long running thread is really needed, then the asynchronous code can spawn one off deliberately (and still without blocking).

If you are using threads to achieve some type of kernel protection between stacks, then I wish you'd just say that. Please don't claim that micro threads are used for scalability when other alternatives are technically more scalable.

I know this is just a rehash of our previous discussions, but it is still a relevant criticism.

Anyways, since you don't mention it, how do you handle the acknowledgement of interrupts? Is this done implicitly by the global interrupt handler? Or is this done within the thread that handles the interrupt?

The reason I ask is if you ack the int right away, then the hardware could fire off another interrupt and have you create a new thread for the same device before the first thread is serviced.

Do you protect from this somehow or do you leave it up to individual drivers?

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