Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
Permalink for comment 474038
To read all comments associated with this story, please click here.
RE[3]: PowerPC v2 ?
by Neolander on Fri 20th May 2011 22:00 UTC in reply to "RE[2]: PowerPC v2 ?"
Member since:

On my first book, it's written "PowerPC User Instruction Set Architecture
Book I
Version 2.02", so I don't have the latest version. This may explain some things.

In the book 3, called "Operating environment architecture", there's a whole chapter (chapter 5) dedicated to interrupt and exception handling. It noticeably mentions an "external" interrupt, that seems to centralize all the external interrupts managed by implementation-specific hardware.

Edited 2011-05-20 22:02 UTC

Reply Parent Score: 1