Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
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RE[4]: PowerPC v2 ?
by DeepThought on Sat 21st May 2011 04:56 UTC in reply to "RE[3]: PowerPC v2 ?"
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2.06 differs between -S(erver) and -E(mbedded) Book III
Both have different exception handling.
But common is, that peripheral interrupts are seen to be "extern" to the core.

On Book III-E CPUs (Core + interrupt controller), interrupts often can be routed to either the traditional "External" or to the new "Critical" interrupt.

In a OS environment, the critical interrupt can be used to bypass the OS completely thus running without jitter.

BTW: On ARM cores other then Cortex-M, the behavior is alike. You have the "normal" interrupt and fast interrupts.
Cortex-M is special, as the interrupt controller is part of the core _and_ the core stacks the registers defined as volatile by the ABI (so ARM argues, you need no assembler anymore).

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