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Member since:
2010-07-17
2.06 differs between -S(erver) and -E(mbedded) Book III
Both have different exception handling.
But common is, that peripheral interrupts are seen to be "extern" to the core.
On Book III-E CPUs (Core + interrupt controller), interrupts often can be routed to either the traditional "External" or to the new "Critical" interrupt.
In a OS environment, the critical interrupt can be used to bypass the OS completely thus running without jitter.
BTW: On ARM cores other then Cortex-M, the behavior is alike. You have the "normal" interrupt and fast interrupts.
Cortex-M is special, as the interrupt controller is part of the core _and_ the core stacks the registers defined as volatile by the ABI (so ARM argues, you need no assembler anymore).