Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
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RE: Locking benchmarks
by jal_ on Sun 22nd May 2011 13:08 UTC in reply to "Locking benchmarks"
jal_
Member since:
2006-11-02

I still argue that a lock free asynchronous model without any threads will easily outperform the "popup thread" model, particularly for simple tasks which consume 1-2K cycles.


This is a very interesting discussion thread, but I'm wondering what kind of model you envision when you talk of a lock-free, asynchronous, thread-less model. Can you point me to a description or more elaborate discussion of such a model?

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