Linked by David Adams on Mon 19th Sep 2011 16:51 UTC, submitted by estherschindler
Intel With the Xeon 7600 line, Intel is finally using the 'R' word: RISC. It's targeting the mission-critical market dominated by Sun SPARC and IBM Power with the new chips, a first. Can the Xeon E7 processor deliver Intel's final blow to the RISC market, which includes its own Itanium?
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tylerdurden
Member since:
2009-03-17

CISC and RISC, and even VLIW, have been meaningless acronyms ever since microarchitecture and ISA became decoupled concepts a while ago.


The average x86_64 CPU tends to a very modern microarchitecture who happens to be able to execute old x86 instructions. Same can be said about SPARC, and POWER for example. Not one of those architectures happen to execute most (if any at all) of their ISA's natively. All of them break them down into micro ops which are not visible to the programmer.

SPARC and POWER, for example, had to do some serious architectural gymnastics in order to allow aggressive superscalar, vector, and out-of-order execution of their original ISAs. Just as intel and AMD has to do with x86.

The main advantage most RISC CPUs had over old CISC designs, in the desktop/high performance areas, was that they offered a cleaner path to 64-bits and marginally faster pipelines... when transistor budgets for logic were still an issue. But that was almost 20 years ago.

Edited 2011-09-20 23:16 UTC

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