Linked by Hadrien Grasland on Fri 30th Dec 2011 08:24 UTC
Hardware, Embedded Systems In the world of alternative OS development, portability across multiple architectures is a challenging goal. Sometimes, it may be intrinsically hard to come up with hardware abstractions that work well everywhere, but many times the core problem is one of missing information. Here, I aim at learning more about the way non-x86 architectures deal with CPU IO ports, and in particular how they prevent user-mode software from accessing them.
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by matako on Fri 30th Dec 2011 17:09 UTC
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Usually whenever you have a CPU with a cache and a MMU, the MMU has the ability to define a page or a segment as non-cacheable, so that R/W operations hit the bus directly. A page can also be locked to physical addressing (no VM translation) and that is pretty much your memory-mapped I/O of the yesteryear.

Typically such facilities are only available in the kernel for hardware driver programming.

Edited 2011-12-30 17:24 UTC

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