Linked by Thom Holwerda on Thu 8th Dec 2005 20:17 UTC
Oracle and SUN If you thought Sun's chip division had already gone mad when they announced and built the Niagara (the UltraSPARC T1), you'll be happy to know that with the first Niagara servers out the door, they haven't exactly been resting on their laurels. Niagara II is on its way: like the T1, it has 8 cores, but now with 8 threads each instead of 4, adding up to a total of 64 threads (the T1 has 32, logically). And, instead of the much-critizised one floating point unit per processor, the Niagara II will feature one floating point unit per core. The chip is set to be released in 2007, at an initial speed of 1.4Ghz.
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by Drumhellar on Sat 10th Dec 2005 04:15 UTC
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Niagra-2 will also integrate an 8x PCI Express, instead of using a J-Bus connection to another chip for PCIe. It will also support SMP, so dual Niagra-2 systems are possible. It'll use a different FB-DRAM for memory, and will probably have roughly 50GB/sec(*) main memory bandwith. Also, multiple 10Gbit ethernet connections are likely(*).

Currently, the FPU on a Niagra has a 40 cycle latency, due to access syncronization and the need to move bytes around the chip. With each core having it's own FPU, the latency should drop quite significantly, so expect a really big gain in floating point stuff.

If all this comes to pass, all I can say is, well, nothing, since my jaw will be on the floor.

*(This is speculation, suggested at )

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