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Its been shown quite explicitly (hah!) that Itanium needs the ridiculously sized caches to perform adequately. It doesn't matter whether the extra transistors are in the caches or in the core --- what matters is the final die size.

Wrong and wrong. If you check out the specint, fp, and 2-way rate for all Madison variants, you will find that the improvement of Madison 9M (400 MHz FSB) over Madison 3M (533 MHz FSB) is less than 10%, and that the much more recent Madison 9M (667 MHz FSB) is in this range as well.

I do not think that 3 MB is in any way ridiculous in a modern process.

The large cache variants exist for the same reason that Potomac Xeon with 8 MB L3 exists -- for multiprocessor machines with a larger than ideal number of CPU's on a single FSB segment. This is a platform issue and has nothing to do with the CPU design.

It seems that you concede this in your last lines, saying that Madison 'only' does 20-30 percent better than Opteron, and that's 'not a lot' for a CPU with worse interconnect technology -- in fact, it seems like this speaks well of the core Itanium2 technology, that it does that much better with a definitely worse memory subsystem.

Furthermore, your claim that only die size matters, and it does not matter whether the transistors are in the core or cache, is patently false. Both because of the regular structure of caches, and because of (in some cases lots of) redundant rows being built in, the % of rejects due to cache problems is way lower than that from core defects--that is, modern (read, all intel) cache designs just don't contribute much to lowering yields. A large die with good yields can easily be at price parity with a smaller one with worse yields.