Linked by Thom Holwerda on Wed 8th Feb 2006 18:24 UTC
Permalink for comment 94205
To read all comments associated with this story, please click here.
To read all comments associated with this story, please click here.
News
Linked by Thom Holwerda on 06/18/13 22:33 UTC
Linked by Anonymous on 06/18/13 22:26 UTC
Linked by Thom Holwerda on 06/18/13 22:25 UTC
Linked by Thom Holwerda on 06/18/13 17:45 UTC
Linked by Thom Holwerda on 06/18/13 17:32 UTC, submitted by poundsmack
Linked by Thom Holwerda on 06/17/13 17:58 UTC
Linked by Thom Holwerda on 06/17/13 17:52 UTC
Linked by Thom Holwerda on 06/14/13 21:03 UTC
Linked by Thom Holwerda on 06/14/13 20:46 UTC
Linked by Thom Holwerda on 06/14/13 17:32 UTC
More News »
Sponsored Links



Member since:
2005-08-09
it's only a question of compiler switches and possibly some assembler-coded routines.
Will some SSE3 specific code run on anything other? So this code is tied to one cpu.
SIMD code may require rearraged data and different algorithms than scalar code.
Also, apps won't be able to take advantage of future Cells with more SPEs
With the right programming model this will be done by OS automatically.
or bigger local memory
This will not happen in a near future. They didn't left the space between SPE local memory area and registers, so they have only one choice: breaking the SPE memory area to 2 pieces.