Linked by Nicholas Blachford on Wed 9th Jul 2003 16:43 UTC
Talk, Rumors, X Versus Y This article started life when I was asked to write a comparison of x86 and PowerPC CPUs for work. We produce PowerPC based systems and are often asked why we use PowerPC CPUs instead of x86 so a comparison is rather useful. While I have had an interest in CPUs for quite some time but I have never explored this issue in any detail so writing the document proved an interesting exercise. I thought my conclusions would be of interest to OSNews readers so I've done more research and written this new, rather more detailed article. This article is concerned with the technical differences between the families not the market differences.
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Way I look at is it really argument of what instruction set you like to program in: ARM, MIPS ALPHA Sparc, PPC, or X86. All of the previous CPU architectures are capable of getting to the Nirvana CPU speed all CPU geeks seek. It just matter of a lot of money, 18 to 48 month of time, getting good experienced CPU micro-architects and Quantum Mechanics (Transistor Tweekers).

What we need to look at is Software Operating system have become stable if not boring, Window2000/XP and Mac OS X are based on research from about late 80ís. Also memory code size limitations of the past are distant memory in the desktop and server space. Which drove feature rich similar O/S Cores. Plus if you remember history True64 Unix (Mach) , Mac OS X(Mach), and Windows NT(Cutler Design ex Dec) are all based on modified micro kernels

What this has done is move all CPU Architecture off their polar position an began rationalizing their ISA to better meet the needs of software evolution to pretty stable foundation based on common C/C++ based Multithreaded, multi-user, operating system to almost a homogenization of feature (Core CPU Instruction, Floating Point Instruction(SP, DP, Parried Single) Debugging Instruction, DSP Like Instructions (Multiply Accumulate, etc), and Vector Instruction the need to better support the market segments and application where they were moving to support.

What this did is put more pressure on CPU Micro-Architects to innovate since their was going to be less innovation coming form ISA extensions. So they had two choice Fast Clock speed Narrow Super-pipelined architecture or wide slower clock high CPI Micro architectures. They had to look at innovative way to deal with memory latencies (Caches, Larger Register Sets, Instruction Buffer, etc) , also understand how best to deal to code control flow issue ( branch prediction) Here is were the visionaries evolved and ALPHA was one of the greatest CPU experimenting environments to emerge in the last 10 years and they tried all the variation ( In-order, Out of Order, Dual Issue, Multi issue, Multithreading, on chip memory controllers and more). Big Issue today all of these innovations drive Gate Count and chip complexity which reduce our ability to make bigger innovation beyond wait for the next process geometry

When compare and contrast the PIV and the 970 they both do something similar. If you want to crank up the clock on the CPU the best way to do this is go with a super-pipelined micro-architecture. And to do this at these new speeds you need to do some thing which Dec invented on the MicroVax Processor and that is to crack PPC or X86 instruction set into simpler instruction (micro-ops). What interesting is Intel been doing this since PentiumPRO. I would argue these Microcodes made Intel more RISC then the current classic ISA level RISC processor. So now that IBM made this leap in Processor design it now back to race to who the best process technology and do most innovative transistors, with minor micro-architecture tweaks . Also with the announcement of Power5/980 Architecture, IBM and Intel are parity of feature again around SMT/HT. Here some of the best research on the subject. (

On the power issue of X86 core look know further then the Pentium M which is one incredible X86 CPU which matches PPC G4 10 Watts 1 GHz with and the bonus of an amazing branch prediction unit, and 1 megabyte of onboard L2 Cache. So this point is moot as well since this Micro-architecture and Quantum Mechanic issue (Transistor tweeker)

If you want to see innovation in CPU architecture look at following project since they are truly driving innovation into again CPU design, Compiler Research and Operating Systems and Application Design To MIT projects are based on MIPS like instruction set.