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Do you really belive that compilers model processors to that detail? They don't. There is no need to do that (and is in reality impossible) to get good performance out of the processor, and that applies for human coders also.
Compilers do model the processor to that level of detail. GCC's code generator uses DFA (Deterministic Finite Automata) instruction scheduler. Each processor has a DFA description called an MD file. These MD files describe the details of the processor's pipelines. The MD file for the i386 architecture is 23,000 lines, plus another 1000 lines for each specific CPU model. Several thousand additional lines of code are dedicated to GCC's register allocator. And the i386 is a relatively lenient architecture!
Precise modeling of the processor is even more important for a processor like IA-64 and PPC-970 that have complex rules for instruction grouping and instruction dispatch. Its even more important on IA-64 which doesn't do any internal reordering or optimization.