Linked by Tony Bourke on Thu 22nd Jan 2004 21:29 UTC
Benchmarks When running tests, installing operating systems, and compiling software for my Ultra 5, I came to the stunning realization that hey, this system is 64-bit, and all of the operating systems I installed on this Ultra 5 (can) run in 64-bit mode.
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@MJ
by Raptor on Fri 23rd Jan 2004 10:06 UTC

Also, since you have larger addresses, your cache footprint increases which means you get fewer lines in the cache. More cache misses == poorer performance as you have to go further down the memory heirarchy to satisfy your requests. As a point of fact, the SPARC v9 architecture only allows you 22-bits for as immediate operand, so to construct a 64-bit constant you have to issue more instructions.

Let's think for a second. The bigger the pointers the less number of cache lines, does that make any sense? The number of cache lines are the same regardless of the bits in an address. A cache line is identified by a tag and 32-bit and 64-bit address will eventually hash down to similar tags thus occupying all the cache lines in the cache. Line size and number of cache lines are always constant for caches.

Sparc uses a 22 bit immediate field only for the sethi instruction. There more ways to construct a 64-bit instruction. At max you will need 3 instructions to build a 64-bit constant.