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Eh, kindof. You're right that there will always be the same number of lines in the cache, but frequently caches are designed so that it is possible to put a number of blocks in one cache line. These blocks are selected by a tag, as you pointed out, and also an index. I should have been more specific, my comments were mostly in regard to the TLB where you will certainly be able to hold fewer blocks if you're using a 64-bit VA instead of a 32-bit VA.
The blocks you mention are always ths same size regardless of the address size. A n-way associative cache on a 64-bit processor will have the same line size and block size regardless of 32-bit or 64-bit adresses being used. The index is the line, say two VAs hash down to line 0 thier index is 0.
TLBs are nothing special, they are fully-associative caches for the MMU if you will. TLBs cache address translations and not data or instructions. The tag protion of the TTE is always the same size regardless of 32/64 bit VAs. The Data section which holds the physical address is also the same size no matter the size of the address.