Linked by Thom Holwerda on Thu 30th Jun 2005 12:27 UTC
Hardware, Embedded Systems There are increasing rumors that Alpha might be brought back to life. The Inq sets the big 'if' aside and explores the possiblities: "What if there really is a will to get Alpha back into the changed market? What sort of chip would it have to be to have that good chance of success, if any?"
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by JJ on Thu 30th Jun 2005 21:23 UTC

Yeh I post on comp.sys.transputer or comp.arch.fpga, trying to keep on a monthly update of anouncements. I have a paper for a sep conference on parallel computing otherwise it will go out earlier on the web when ever they make up their minds.

Funny you should mention that 3d ray tracer, thats been brought to me before by someone else that helped me out on the architecture thinking. It does look like nVidia ATI may be way over the top as well as the cpu guys. Sometimes working on a shoestring helps clear the air and think about how to do things in a different way.

My burden is doubled because I must also do the C compiler which adds in occam and some of Verilog to allow the processor to be programmed in the par language I'd like to use. GCC, and or Pthreads would hardly be any good. Inmos had the same burden with occam.

FPGA processors are quite doable today but the rest of the crowd are all doing 120MHz or much slower basic RISCs about as simple as you can do and suffer from the real limits of FPGA at making logic decisions in line with the instruction decode every cycle. ASICs get it 3-5x better than FPGAs and full custom VLSI that Intel,AMD,IBM get another 2-3x on top. But FPGA memories are quite fast. The 4 way 2 cycle threading I use allows for the FPGA to make its bra type decisions and spread it over 8 pipe stages instead of just 1 stage so it just runs and runs, and stalls are relatively small and limited to each thread. I have an FPGA board (Xilinx starter sp3 200) and thats good enough to prototype. The Processor Element (not quite finished) has gone through P/R upto 300MHz (high end V2Pro) and compares with an XP300 if that existed. The MMU is at conceptual design still but has gone through C simulations.

The threading approach I, Raza, Niagara use all help to bust through the usual complexity of cpu design and replace it with another type of more manageable complexity. No one AFAIK is trying to do process and message support in the HW today ala Transputer and certainly no one is thinking of bringing the MMU to help the management of user objects.

The long term goal is to bring back the TRAM idea, each mini credit card module has an FPGA and DRAM with a few or many cpus inside with some other function on the side such as NIC, XVGA, PCIex etc. One then combines these cards to build a system with as many features as you want, connected with serial links. Other folks esp in Germany are doing some amazing FPGA boards.

Patents I am not too worried about, everthing has already been done before, I just put it back together again like humpty dumpty.

I can be reached offline at the usa address.