Linked by Thom Holwerda on Thu 30th Jun 2005 12:27 UTC
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There's actually nothing really wrong with the Itanium
How about VLIW and EPIC?
Very large instruction words, with 43 bits per instruction in the Itanium case, unsurprisingly require very large instruction caches to hold them.
Explicitly parallel instructions sound good in theory, but ignore the fact that memory latencies in today's cache hierarchies are quite unpredictable, so that a dynamic instruction scheduler can do a much better job than a static one.