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Raptor, he's referring to the way Intel maps the CISC instruction set to RISC instructions internally on the latest Pentiums. I'm guessing there is no way to bypass the CISC instruction decoder. The existance of a uniform instruction format for the RISC microcode is extremely unlikely.
lipstick lesbian, the Itanium has a LOT more going for it than just VLIW (even though the VLIW in Itanium is a complete waste unless you're using a compiler that optimizes for explicit paralellism). I agree the Itanium sucks, for different reasons, but Transmeta has a looooong way to go to compete with the raw power of the Itanium.