Linked by Nicholas Blachford on Sun 10th Feb 2002 17:37 UTC
Editorial "This will end up being one of the world's worst investments, I'm afraid," - David House, former Intel chief of corporate strategy said in the early 1990s. I've been fasinated by microprocessors for years and have been following the Merced debacle since back in 1994 when HP and Intel announced they were getting together to make some amazing new technology.
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One of the reasons I promote this dual approach is (a) smooth transition for (b) long term performance gains.

MDRONLINE estimates a 2% compounded penalty for using x86 ISA. - one that would be remedied to a switch with either RISC or VLIW.

let's look at apple as a case example. Apple started on CISC, the 68k line. they then switched to powerpc, with a 68k emulator. now they are almost native 100% RISC.

continually extending x86 maybe challenging. one of x86 problems is small register set (8).

let us suppose that amd allowed for a compiler that directly coded to its RISC engine.

AMD can claim fast x86 execution. this would be like apple powerpc emulating 68k. they can also claim speed improvements with certain applications by writing specifically for its RISC core in micro-op. This would be like writing for apple's powerpc native code.

at some point, if there is the demand, amd can offer cpu that are very powerful, and will run only with its RISC core. this will reduce die size and heat and transitor count and improve performance.

The Althon engine is purely internal and there is no reason for AMD to expose it even if they could. The big selling point for Athlon is compatibility with legacy applications. If AMD exposed the engine they would have a RISC chip, but one that isn't compatible with any existing processor architecture and which doesn't have any software. Take it from someone who's been there / done that, there are better ways to throw away money.