Submitted by “Hoping to improve the state of server software, Sun Microsystems has confirmed that it will include support for transactional memory with the first generation of its Rock processors due out in the second half of next year. Sun’s research and development teams have spent years working on a type of transactional memory that combines software and hardware aids. Now, the company looks set to be the first mainstream chip maker to build transactional memory hooks into its chips.”
Just curious someone can give an executive summary. At a glance, this looks, kinda, like “Optimistic Locking” only with RAM vs databases.
Is that a reasonable 30,000 foot back of napkin one liner that describes Transactional Memory and how it would be used?
I hope this helps.
http://en.wikipedia.org/wiki/Software_transactional_memory
Edited 2007-08-22 21:32
There was some discussion of this generated within the Intel Technical Journal thread last week. I think I might have triggered it (tee hee). Would’ve been nice for OSNews to write the article first, rather than link to other sites articles all the time.
Having said that, perhaps I should have submitted an article, is that possible?
Edited 2007-08-22 19:03
Would’ve been nice for OSNews to write the article first, rather than link to other sites articles all the time.
…? I don’t get what you mean.
Intel finally released the new issue of ITJ, so now we can usefully discuss it.
http://www.intel.com/technology/itj/2007/v11i3/index.htm
A few months ago, OSNews linked to something on the TRIPS processor, which is multi-core and uses dataflow as the programming model, generally speaking. It has many similarities, it seems, to what’s proposed here, in that the TRIPS processor executes a chunk of instructions, and either the final results are committed or they aren’t, in a single transaction for that set of instructions and data dependencies.
It may end up being that regardless of which method is superior long-term, that the one first with commercially-produced hardware and software support will be the winner and largely determine how and what is used, or perhaps many things will be combined, and something better than any single thing will be adopted. It sounds more and more like what my future kids will learn about when it comes to developing software will be notably different in many ways from what I learned, regardless.
Studies of INTEL shows that a typical x86 CPU idles 60% under full load, because of cache misses. All CPU’s have this problem – except SUN’s new family of SPARC cpus. They idle less than 10%, more likely 5%. Therefore they are wicked fast on some multithreaded workloads. They are slower on a single thread. But, as SUN is targeting the big Enterprise market, who runs a server with only one thread? Not that important in my opinion. The existing T1 and T2 cpus are lowend CPU’s. Next year the ROCK will arrive, which is a really highend CPU. We live in interesting times.