OSNews: http://www.osnews.com/story/18492/Sun_Slots_Transactional_Memory_Into_Rock Exploring the Future of Computing en-us Copyright 2001-2013, David Adams adam+nospam@osnews.com Sat, 25 May 2013 11:58:28 GMT http://www.osnews.com/images/osnews.gif OSNews.com http://www.osnews.com Anyone know anything about this? http://www.osnews.com/thread?265024 http://www.osnews.com/thread?265024 Just curious someone can give an executive summary. At a glance, this looks, kinda, like "Optimistic Locking" only with RAM vs databases.

Is that a reasonable 30,000 foot back of napkin one liner that describes Transactional Memory and how it would be used? Wed, 22 Aug 2007 18:46:00 GMT donotreply@osnews.com (whartung) Comments as previously reported on OSNews last week ;) http://www.osnews.com/thread?265029 http://www.osnews.com/thread?265029 There was some discussion of this generated within the Intel Technical Journal thread last week. I think I might have triggered it (tee hee). Would've been nice for OSNews to write the article first, rather than link to other sites articles all the time.

Having said that, perhaps I should have submitted an article, is that possible?Edited 2007-08-22 19:03 Wed, 22 Aug 2007 19:02:00 GMT donotreply@osnews.com (horsnell) Comments RE: as previously reported on OSNews last week ;) http://www.osnews.com/thread?265031 http://www.osnews.com/thread?265031 Would've been nice for OSNews to write the article first, rather than link to other sites articles all the time.

...? I don't get what you mean. Wed, 22 Aug 2007 19:07:00 GMT donotreply@osnews.com (Thom_Holwerda) Comments RE: as previously pre-reported on OSNews last week ;) http://www.osnews.com/thread?265046 http://www.osnews.com/thread?265046 Intel finally released the new issue of ITJ, so now we can usefully discuss it.

http://www.intel.com/technology/itj/2007/v11i3/index.htm Wed, 22 Aug 2007 20:10:00 GMT donotreply@osnews.com (Wes Felter) Comments RE: Anyone know anything about this? http://www.osnews.com/thread?265069 http://www.osnews.com/thread?265069 I hope this helps.

http://en.wikipedia.org/wiki/Software_transactional_memory

In computer science, software transactional memory (STM) is a concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It functions as an alternative to lock-based synchronization, and is typically implemented in a lock-free way. A transaction in this context is a piece of code that executes a series of reads and writes to shared memory. These reads and writes logically occur at a single instant in time; intermediate states are not visible to other (successful) transactions. The idea of providing hardware support for transactions originated in a 1986 paper and patent by Tom Knight.
Edited 2007-08-22 21:32 Wed, 22 Aug 2007 21:31:00 GMT donotreply@osnews.com (flanque) Comments I don't know which happened when, but... http://www.osnews.com/thread?265073 http://www.osnews.com/thread?265073 A few months ago, OSNews linked to something on the TRIPS processor, which is multi-core and uses dataflow as the programming model, generally speaking. It has many similarities, it seems, to what's proposed here, in that the TRIPS processor executes a chunk of instructions, and either the final results are committed or they aren't, in a single transaction for that set of instructions and data dependencies.

It may end up being that regardless of which method is superior long-term, that the one first with commercially-produced hardware and software support will be the winner and largely determine how and what is used, or perhaps many things will be combined, and something better than any single thing will be adopted. It sounds more and more like what my future kids will learn about when it comes to developing software will be notably different in many ways from what I learned, regardless. Wed, 22 Aug 2007 21:58:00 GMT donotreply@osnews.com (JonathanBThompson) Comments SUN first again http://www.osnews.com/thread?265181 http://www.osnews.com/thread?265181 Studies of INTEL shows that a typical x86 CPU idles 60% under full load, because of cache misses. All CPU's have this problem - except SUN's new family of SPARC cpus. They idle less than 10%, more likely 5%. Therefore they are wicked fast on some multithreaded workloads. They are slower on a single thread. But, as SUN is targeting the big Enterprise market, who runs a server with only one thread? Not that important in my opinion. The existing T1 and T2 cpus are lowend CPU's. Next year the ROCK will arrive, which is a really highend CPU. We live in interesting times. Thu, 23 Aug 2007 09:55:00 GMT donotreply@osnews.com (Kebabbert) Comments