posted by Thom Holwerda on Fri 24th Aug 2018 22:32 UTC
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In essence, it's a 32-bit RISC ISA designed from a holistic view on integer, floating point, scalar and vector operations. In addition there is a hardware implementation of a single issue, in order, pipelined CPU. The hardware implementation mostly serves as an aid in the design of the ISA (at the time of writing the CPU is still incomplete).

As happens with some articles I post here, this one's definitely a bit over my head.


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