http://www.osnews.com/story/6258/Reporting_from_the_VLSI_Symposium Exploring the Future of Computing en-us Copyright 2001-2012, David Adams adam+nospam@osnews.com Wed, 15 Feb 2012 14:55:36 GMT http://www.osnews.com/images/osnews.gif http://www.osnews.com http://www.osnews.com/thread? http://www.osnews.com/thread? I'm not a hard core VLSI engineer or anything, but I've done some layout, and I think an area where things can still be tremendously improved space-wise is contacts. Contacts take quite a bit of space on a transistor, while they remain in the shadow of the gate length. If contact resistance could some how be significantly reduced, then transistors overall area could be significantly reduced. Sat, 06 Mar 2004 06:38:00 GMT donotreply@osnews.com (Anonymous) Comments http://www.osnews.com/thread? http://www.osnews.com/thread? most univs and schools dont have the best facilities.. if that is also improved.. the boom will be better;
cheers
ram Sat, 06 Mar 2004 13:46:00 GMT donotreply@osnews.com (Anonymous) Comments http://www.osnews.com/thread? http://www.osnews.com/thread? Dr. Eshraghian is a giant in VLSI esp the book area but with VLSI fabs, masks, EDA tools all going out of the stratosphere, there surely can't be much interest anymore in teaching VLSI routinely to potential EEs.

Pleasure to reads his thoughts again, but few surprises for an insider.

Luckily most of what an EE student could ever want to do can be done pretty well with the newest FPGAs. That doesn't help those with more interest in analog or mixed signal or nano scale, but it gets the big $ out of teaching logic design in a big way.

The free SW I am using allows me to do cpu design I could never have realised with regular VLSI tools. And with a PC priced development board I will be up and running or bust.

Ofcourse there is still MOSIS and other wafer shuttle runs, but the best technology is still 4-5 figures for protos which still keeps out most edu depts.

The really hard stuff will end up back in the pyhsics dept where it all came from, kind of sad that most EEs are getting pulled away from the bleeding edge.

When I started out, transister design was alot of fun and very inventive beig NMOS with all its limits to overcome. I even was given all the fab details I didn't really quite need to know. The CMOS switch was obviously a lifesaver for the industry but less chalenging until CMOS started to hit the wall too. Thats the way it goes, FPGAs just the next turn of the wheel.

johnjakson_usa_com Sat, 06 Mar 2004 16:02:00 GMT donotreply@osnews.com (Anonymous) Comments http://www.osnews.com/thread? http://www.osnews.com/thread? I was a 1st year EE student in 1981 at the University of Adelaide, where Dr Eshraghian taught us introductory digital logic and we had practical work doing machine code programming on Intel 8080 based single board computers. At the time we knew that Dr Eshraghian was a good teacher, but his work on technologies such as mobile video telephones was still in the future. It was good to read that he is still on the bleeding edge. Sun, 07 Mar 2004 13:02:00 GMT donotreply@osnews.com (Anonymous) Comments http://www.osnews.com/thread? http://www.osnews.com/thread? The MOS technology features auto-alignment : The gate oxyde is used to mask the substrate during the doping process ( N wells ). The width of the gate ( and thus the length of the channel ) is so the most characteristic figure of a given technology. Mon, 08 Mar 2004 09:30:00 GMT donotreply@osnews.com (Anonymous) Comments