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Many of the remaining speakers for the morning were also presenting papers on technologies which were not fully or even remotely MOS based. A paper on nanotubes used as large PLAs (programmable logic arrays) was given which was most interesting, but it did have a few "bugs" to work out. A professor from Georgia Tech presented a paper on a nanoscale computational building block which also looked very promising as a replacement for standard MOS. His paper also noted a recourring theme which I have seen around the net and in papers as of late which is the automatic generation of cells by a chemical or biological growth. Basically, a standard cell is grown in the lab, and then it is repeated or made to grow into an array. The cell itself can perform a basic function, and of course when put into an array or added to many others, we can provide basic logic functions from the arrangement of them. After all, this is how the basic building block of any large scale circuit is done. We build a basic block with simple functionality, and figure out how to get greater functionality through a combination of them. Then a mere optimization of the basic block will result in speed increases or power reduction or whatever your target is for the entire circuit (of course, this is given that the function is optimized from the start).

To summarize, most of the presentations were on "the usual" if I can even say that, meaning they were on power optimization, layout, routing, area and cost, pipelining, etc. Of course, all of them were great in their respective fields, but again, most people would be bored unless you are into each one specifically. If you would like to get a copy of the papers presented see [1].

My thoughts on the future of design: Of course we will reach an end to shrinking transistors, but this is not the end for the designer. It has been noted that the general purpose CPU accounts for only 2%-10%of total CPU sales. The remaining 90-98% are in embedded systems [4][5]. The future of computing has been theorized and continues to be, but the reality of the now is that the majority of devices use small CPUs which are not as powerful as their desktop brothers. It seems this trend is making its way into the personal arena in terms of computing also (wearables, PDAs with more and more functionality, smaller and smaller laptops, etc). The designer of tomorrow still has choices, they can go into emerging technologies such as nono, optical and biological (or a meld of any of them) or delve into getting more out of less with embedded systems and SOCs (System on a Chip). Also, the separation of software and hardware engineers is becoming smaller as we move into the embedded space. Hardware is useless without software and vice-versa. But in the embedded arena, memory and CPU time is as it was many years ago, precious. Those devices are less powerful and have less memory (for example, the extreme of smart dust research, or the more popular wearable computer). Programmers will have to revert back to optimizing everything (as it has been noted that in todays personal computers we have plenty of power, and programmers can be a little bit more lazy given the average hardware), not that I am saying todays programmers are lazy, just that in the embedded space or days of old, they were forced to be optimal in their ways.

Length and Width: confusion

I have seen many news sites and others try to explain the number that CPU manufacturers give when they talk about a CPU technology. Some are correct, and some are just confusing. I must admit, however, that having been a student of Physics and taken solid state physics, I myself get confused due to the fact that what part the engineers call the width, we call the length and vice-versa. However, I will let you in on it right here and now. When a manufacturer says that they are using a 90 nanometer process, or equivalently a 0.09 micrometer process, what they mean is that the channel length of the transistor is 90nm. Or what is commonly stated is "the smallest device I can create on the substrate is 90 nanometers". This is for the simple fact that to create a transistor on a substrate we must implant the substrate with a "P" or an "N" well, and then pass a polysilicon line over it (creating the gate of the transistor). The gate of the transistor dictates the minimum size of the transistor (or conversely, the minimum distance in between two ends of a transistor, which is where the gate is :). So fundamentally, the minimum feature size is the gate of the transistor, and this is the number they are referring to. It is not the entire transistor, although one could argue that the gate is where all the action is.

In the above oversimplified handmade diagram is a cross section shot of a transistor with the width labeled W and the length labeled L. It also shows two N wells, the gate oxide under the gate, and the substrate. To put that huge figure I presented into perspective, (if the numbers I have read are correct) the AMD Opteron contains 110 million such transistors (although some are P and some are N types) and the latest offering from the ATI radeon line is reported to contrain 150 million transistors.

References:

[1] Catalog
[2] Principles of CMOS VLSI Design, A systems Perspective. Neil H. E. Weste, Karmran Eshraghian, 2nd edition, 1995.
[3] Story
[4] http://www.cs.virginia.edu/~pnn7f/vest/
[5] http://www.nd.edu/~codes/index.html

1. "VLSI Symposium, Page 1/2"
2. "VLSI Symposium, Page 2/2"