Speculative Exaltations
There is pretty much zero public data available on the project other than it will almost certainly be dual core. However there are general industry trends and other announcements which may shed light on what this processor might look like.
The following is thus speculation...
The POWER5 and Opteron both have on-die memory controllers, a feature which is, in my opinion, a good bet to be included, especially given Intel and Freescale are already planning to add memory controllers to their CPUs. An on-die memory controller alone will have a considerable performance impact as it will reduce memory latency (the delay between when data is asked for and when it arrives).
HyperTransport is another possibility, IBM are a member of the HyperTransport consortium [6] and already use the technology on the existing 970's northbridge. This would be an important cost saving measure as it would save IBM from needing to spend millions on developing another northbridge. Using HyperTransport as the link technology means standard PC parts for the Athlon 64 can be used in 9x0 systems.
This would also save other PowerPC manufacturers the pain of sourcing PowerPC specific northbridges which can be a royal pain as the only available parts are generally for the embedded sector and these are often not quite what a desktop manufacturer wants.
The CPU will most likely be made using a 90nm process in a less conservative manner than the POWER5 so it will run faster and cooler. Quite how fast it will be able to run is open to question and I think it's fairly likely IBM will go the same route as AMD in their dual core plans and not clock the processor as high as possible to keep power consumption within reasonable limits. This will not be easy as POWER5 consumes 160 Watts at 1.8GHz (power consumption isn't much of an issue at the high end).
One possibility is to use the same technique the POWER5 already uses which is to constantly adjust the clock frequency to keep heat output down. This technique is becoming popular with Transmeta and Intel doing or planning to do the same.
Another possibility would be to use a technique Intel plan to use for the next Itanium "Montecito," which includes two peltiers in the heat sink. Peltiers actually consume quite a bit of power themselves but reducing the CPU temperature reduces transistor leakage, this lowers the power consumed by the CPU itself allowing boosts in clock frequency which might not otherwise be possible.
Montecito is expected to consume 100 Watts but its heat sink requires a further 75 watts. The end effect is overall power consumption does not change (it may even go up) as part if moved to the heat sink but the CPU itself does not get so hot when working. AMD have filed a patent on an on-chip peltier so they're evidently considering similar technology.
I don't know if the 9x0 will be so hot as to require such aggressive cooling but things are heading that way. "Power density" is becoming a problem and will seemingly only get worse in the future. Power density is the heat generated in a specific area; as CPUs get ever smaller the heat is generated in a smaller area and thus the unit becomes progressively more difficult to cool. The 970FX used in Apple's PowerMacs actually uses less power than the previous 970 but liquid cooling was added because of the higher power density.
Vector Move?
One long-rumoured feature of the 9x0 is the addition of new vector instructions (read Altivec 2). Altivec is the most powerful feature of the PowerPC line. The G4 is pretty modestly clocked, by x86 standards, to keep power consumption down, but they more than make up for it when Altivec is activated. The original architecture was designed by Keith Diefendorff at Apple and word has it he has returned to the company so it's possible a new version is in the works. Whether it will make it into a G6 is open to question but early information on the POWER6 seems to indicate that processor will include vector processing capabilities.
What an enhanced Altivec would do is another question. The architecture could be extended to support 64 bit floating point operations. Another possibility would be to double the width doubling throughput; additional registers would also increase performance in some areas. However these are just guesses, the reality could be very different.
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