Linked by Eugenia Loli-Queru on Wed 22nd Mar 2006 18:08 UTC
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ASM programming knowledge is evanescent. Your ASM programmer friend is right that the XOR form can avoid partial register stalls, but only on the P6 core, which is prone to them. On that architecture, reading a 32-bit register after writing to that register's 16-bit lower half will cause the processor to stall, except with XOR or SUB. So depending on whether eax is ever read in the above fragment, the XOR form could be faster, but only for the P6 core. No other current x86 core (including P6-derivatives like the Dothan or Yonah cores), suffer from this specific case of partial register stall.






Member since:
2005-07-06
An ASM programmer.
In the p4 manual is when they started recommending using mov wax,0 because of register stall issues. Or you can pair op codes a certain way.
I don't believe it had to do with actual clock cycles so much as register stalls and surrounding code.