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2) Some great things about the G5 architecture:
1) The processors have a very small pipeline, so a 2.5GHz G5 runs much faster than a 2.5GHz Pentium.

The G5 actually has a very long pipeline. At 16 stages, it's 33% longer than the pipeline on an Opteron or Pentium Pro. It also has a 2-stage integer execution pipeline, which is twice as long as the integer execution pipeline on most CPUs.

In practice, the G5's IPC isn't that great. It's quite good for floating-point code, but on integer code, but not so great for integer code. It gets 575 SPECint/GHz. That's a little better than a Pentium 4 (which at least scales to very high clockspeeds), but much lower than an Opteron (750), Core Duo (800+), or Core Duo 2 (1000+).

2) 64-bit. New Intel based Macs are 32-bit as far as I understand

Which would be great if OS X supported it for more than CLI apps.

3) DDR2 memory is great. The Intel Macs of course have this as well, but it is no reason for me to switch to an Intel because I already have it.

DDR2-667+ is great. The PowerMac uses DDR2-533. That's a speed-grade where DDR2 doesn't clock higher enough than DDR1 to make up for its inherently higher latency.

The PowerMac G5 is a very solid machine (I love mine), and throwing 4 cores in a system will make up for a lot of inefficiency, but its not a great design. Apple designed a pretty shitty memory controller for it, which hurts it a lot in practice. Moreover, it's the first-gen iteration of the Power4/5 core, and as such its missing a lot of the improvements that IBM made in Power5 to improve its integer IPC (from ~600 to ~800).

Smaller pipeline=less time to refill=faster

That's essentially false.
1. A 2.5 Ghz G5 doesn't run faster than a P4 2.5 Ghz because of the (length of the) pipeline (if at all). The PowerPC 970MP (G5) has a 16 stage-pipeline, while the P4 had a 20 stage-pipeline (later 31) and the new Intel Macs (Core Duo) have a 12 stage-pipeline.
2. A pipeline is built for speed, that is, the longer (or deeper) the pipeline, the faster the execution (a greater number of instructions completed per second, throughput). It's true that in cases of branches the pipeline must be emptied, but branch predictors and code reordering reduce the time misused.

As a conclusion, it is generally known that Intel regretted the excesive depth of the P4 pipeline, so they reduced it in new processors. Following the "minimum pipeline" ideology, you should go for a new Intel Mac.

EDIT: wrote at the same time that rayiner's comment

Edited 2006-07-16 01:08

I think the Intel design is often unfairly maligned.

Netburst was based on some research that suggested that if you look at the trade-off between the IPC loss afforded by long pipelines versus the increased clockspeed afforded by long pipelines, the sweet-spot was a lot higher than the 10-12 pipe stages found in most processors. Indeed, they found the sweet-spot somewhere around 50 pipeline stages.

The problem with the design was a combination of an over-ambitious design, and some process-technology limits that they couldn't have predicted. What really killed them was the scaling issue, of course. The Northwood P4 scaled to 3 GHz at 130nm. Using the traditional frequency scaling factor of 1.3 per process shrink, it should be running at 5 GHz by now, on a 65nm process. At 5 GHz, it'd get a SPECint of about 2500, which would've been quite good. Of course, they could never even get to 4 GHz, but its unreasonable to expect them to have predicted that at the time.

They also did make some mistakes in the design, in retrospect. Pipelining isn't a perfectly efficient process. Splitting certain tasks over multiple pipeline stages results in control hazards that lower IPC beyond what you'd expect from the extra branch misprediction penalty. There are ways to solve these issues, but each of the fixes is a PHD thesis or two, and there is no way you can stuff that much new tech into a single design. The trace cache probably wasn't a great idea either. Trace caches were originally designed to increase the instruction fetch bandwidth available to a wide OOO core. The P4 was a relatively narrow core, so that advantage was largely unused. Instead, it was used mainly as a technique to allow the storage of predecoded x86 uops, but given the relatively large size of a uop, and the 2-3x overhead of a non-clever trace cache design (again, another PHD thesis or two), as well as the rigorous cycle time requirements of the P4, which necessitated relatively small caches to begin with, it wasn't very well suited for the design.

Mate, there is no use trying to explain basic facts to the PowerPC fanboys. Intel acknowledged the flaws in its Netburst design and as such, with the Core 2, made a radical change in direction.

The new processor has a 14 stage pipe line, bigger cache, can complete one SSE instruction pet clock cycle rather than taking 2, there is micro-op fusion, faster front side bus (1066Mhz).

By enlarge, Intel has not only come back to beat AMD, but also justifies Apple's switch to Intel, couple that with the vastly improved 965 graphics chipset, Steve Jobs can rightly sit on his throne with a smug face saying, "I told you so".

Well then thank you and rayiner for correcting my misunderstandings! I think I will go and buy a new Intel Mac ... but no too soon - I will wait probably a year after the Intel PowerMacs come out (for money purposes, and to get a second revision)