Linked by Thom Holwerda on Fri 29th Dec 2006 21:35 UTC
IBM Judging by details revealed in a chip conference agenda, the clock frequency race isn't over yet. IBM's Power6 processor will be able to exceed 5 gigahertz in a high-performance mode, and the second-generation Cell Broadband Engine processor from IBM, Sony and Toshiba will run at 6GHz, according to the program for the International Solid State Circuits Conference that begins February 11 in San Francisco.
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RE[6]: Uh-Oh
by andrewg on Sat 30th Dec 2006 19:25 UTC in reply to "RE[5]: Uh-Oh"
Member since:

Hi Rayiner. Not going to try and contradict you but I read through the link ( posted by Dubhthach which was very good. It went over a presentation on Power6 by IBM.

So interesting points.

1. The Power6 does seem have been designed to allow a lot of configurability.

"From the start, IBM has designed the POWER6 systems to be extremely configurable. The intra-node busses, which normally operate on 8 bytes/cycle can be chopped down to 2 bytes/cycle for low-end systems, and the inter-node busses can also operate at 4 bytes/cycle. Similarly, the two integrated memory controllers can both operate at half-width, and one of them can be removed entirely. The external L3 caches are optional, and are available either in the MCM, or in an external configuration. ..."

Now I realise that does not mean it would scale to a consumer level notebook but it is interesting.

2. It appears that Power6 will be better at out of order execution thanks to a change to configuation of pipline stages,

"The basic pipeline for the POWER6 is the same number of stages as the POWER5, but they have been rebalanced across the different phases. Most significantly, dependent ALU operations now can execute back to back, eliminating a vexing kludge in the original POWER4/5 architecture. This makes the out-of-order scheduling easier, and is probably the reason that the instruction issue/dispatch phase uses 2 cycles in the POWER6 (compared to 4 in the POWER5)."

Reply Parent Score: 1

RE[7]: Uh-Oh
by rayiner on Sat 30th Dec 2006 20:27 in reply to "RE[6]: Uh-Oh"
rayiner Member since:

There is a really informative new presentation on Power6 here:

It reveals some details that I haven't seen published before, specifically the fact that the core isn't really any narrower than Power5+: Power6 has 2 integer units, 2 FPUs, one branch unit, presumably 2 load-store units because of the dual-ported data cache, and is 7-issue over two threads and 5-issue on one thread.

In response to your point, you're right that Power6 seems very scalable for IBM's server line. It looks like its going to go from blade systems all the way up to very huge servers. However, the thing to keep in mind is that even the cut-down configuration of Power6 puts it in the high-end Opteron/Xeon range from a system architecture point of view. A half-width memory bus on one controller is still in quad-channel FB-DIMM territory, and even a quarter-width elastic I/O bus is still in Hypertransport territory. And of course the core is still huge, with 4MB of L2 per core, and on-chip L3 directories, etc. Such a system is pushing it even for a hypothetical $5000-range PowerMac, much less a $1500 iMac ;)

Reply Parent Score: 2

RE[8]: Uh-Oh
by andrewg on Sat 30th Dec 2006 21:14 in reply to "RE[7]: Uh-Oh"
andrewg Member since:

Maybe smaller still. If I remember correctly it can be configured without L3 and the L2 cache is twice the size of the admittedly big 2 meg per core cache found on the current Core 2 Duo chips - some of them anyway.

I realise that Apple really had no where to turn, they had to go with x86 or end up using chips which were designed with other purposes in mind. Actually they had already been doing that for years and it was starting to hurt and get worse.

But it is also interesting to see that the Power6 comes with Altivec. Does Altivec have much use in servers or more accurately server application software?

Reply Parent Score: 1