Linked by Thom Holwerda on Tue 22nd May 2007 00:15 UTC
IBM finally took the wraps off its much anticipated Power6 microprocessor, which company executives said will double the clock speed of its current Power5 chip, without stretching the power envelope. The Power6 processor, unveiled at an event on May 21 in London, is a dual-core chip with a top clock speed of 4.7GHz, double the 2.3GHz of the Power5+ processors. The new chip also includes 8MB of L2 cache - four times as large as the current Power5 offering - and an internal bandwidth of 300GB per second. Ars' John 'Hannibal' Stokes obviously also has his say.
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Member since:
2005-07-06
First you're cheating with x86-64: x86 sucks bad, x86-64 is only not very good.
Cheating how? I didn't say anything about x86, just x86-64. And x86-64 is very much in the same spirit as x86.
Comparing the byte length of instructions is only one metric, CISC's variable length encoding makes it more difficult to decode
And who says ease of decode is the most important metric? Maybe it was once, when CPUs were much simpler beasts, but now?
which means that for a similar amount of money, a CPU maker would develop a RISC CPU with better performance than a CISC CPU.
I'm skeptical. x86-64 code can be half the size of PowerPC code. Saving a few pipeline stages in the decode step is unlikely to offset the cost of effectively halving the size of the instruction cache.