Linked by Thom Holwerda on Tue 22nd May 2007 00:15 UTC
IBM IBM finally took the wraps off its much anticipated Power6 microprocessor, which company executives said will double the clock speed of its current Power5 chip, without stretching the power envelope. The Power6 processor, unveiled at an event on May 21 in London, is a dual-core chip with a top clock speed of 4.7GHz, double the 2.3GHz of the Power5+ processors. The new chip also includes 8MB of L2 cache - four times as large as the current Power5 offering - and an internal bandwidth of 300GB per second. Ars' John 'Hannibal' Stokes obviously also has his say.
Thread beginning with comment 242759
To view parent comment, click here.
To read all comments associated with this story, please click here.
RE[9]: Process Technology
by rayiner on Wed 23rd May 2007 20:31 UTC in reply to "RE[8]: Process Technology"
rayiner
Member since:
2005-07-06

Globals are rarely used in any sane c++ code.

And of course C++ is the only programming language anybody ever uses...

In languages that don't suck, it's quite useful to have quick access to various global data structures, often utilized by the runtime.

That said, full-size immediates are not always needed. However, the x86-way of handling immediates is a lot cleaner than the typical RISC-y "load 13 bits of a register at a time" method.

Reply Parent Bookmark Score: 2

RE[10]: Process Technology
by viton on Wed 23rd May 2007 21:44 in reply to "RE[9]: Process Technology"
viton Member since:
2005-08-09

In languages that don't suck
Ohh, can you show the list here?

it's quite useful to have quick access to various global data structures, often utilized by the runtime.

I don't think this is a clever solution.
Anyway RISCy solution for this is Global Pointer.
Actually the lack of global pointer and absolute addressing forces to use various tricks to enable reentrant code with global variables.

However, the x86-way of handling immediates is a lot cleaner than the typical RISC-y

If you need (most likely) to operate on full register width on x86-64, immediate will be 32 or 64bit, even if only few bits are used.

8B0425 01000000 movl 1, %eax
030425 9CFFFFFF addl -100, %eax
4C8B1425 01000000 movq 1, %r10
4C031425 9CFFFFFF addq -100, %r10

In every case of small immediate, RISC instruction is twice as small.

Edited 2007-05-23 21:47

Reply Parent Bookmark Score: 1

RE[11]: Process Technology
by bariole on Wed 23rd May 2007 21:57 in reply to "RE[10]: Process Technology"
bariole Member since:
2007-04-17

"Ohh, can you show the list here?"

Java for example. It's full of them.

Reply Parent Bookmark Score: 1

RE[11]: Process Technology
by rayiner on Thu 24th May 2007 01:04 in reply to "RE[10]: Process Technology"
rayiner Member since:
2005-07-06

Ohh, can you show the list here?

ML, Lisp, Smalltalk, dozens of others. Generally, there is a pretty strong correlation between "not sucking" and needing extensive runtime support services.

If you need (most likely) to operate on full register width on x86-64, immediate will be 32 or 64bit, even if only few bits are used.

Most x86 instructions have a form that sign-extends an 8-bit immediate. MOV doesn't, but loading a small immediate is an uncommon operation in an ISA in which almost all arithmetic instructions take general immediate operands.

Your examples are all very poorly encoded. You've got unnecessary modrm and sib bytes in there.

8B0425 01000000 movl 1, %eax

My assembler gives B8 01 00 00 00 (5 bytes)

030425 9CFFFFFF addl -100, %eax

I get 83 C0 9C (3 bytes)

4C8B1425 01000000 movq 1, %r10

My assembler gives 49 BA 01 00 00 00 00 00 00 00 (10 bytes), but there is a 7 byte encoding (I should fix that).

4C031425 9CFFFFFF addq -100, %r10

49 83 C2 9C (4 bytes)

Reply Parent Bookmark Score: 2