Linked by Thom Holwerda on Mon 20th Aug 2007 19:20 UTC
Hardware, Embedded Systems "A new startup out of MIT emerged from stealth mode today to announce that they're shipping a 64-core processor for the embedded market. The company, called Tilera, was founded by Dr. Anat Agarwal, the MIT professor behind the famous and venerable Raw project on which Tilera's first product, the TILE64 processor, is based. Tilera's director of marketing, Bob Dowd, told Ars that TILE64 represents a "sea change in the computing industry", and the company's CEO isn't shy about pitching the chip as the "first significant new chip architectural development in a decade". So let's take an initial look at what was announced about TILE64 today, with further information to follow as it becomes available."
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RE[2]: ?? instruction set ??
by Kroc on Mon 20th Aug 2007 20:28 UTC in reply to "RE: ?? instruction set ??"
Member since:

If anything x86 isn't exactly a great architecture, just "good enough". If you've tried programming it, you know that even 6502 is more elegant.

PPC, ARM, MIPS &c are all excellent architectures which can be programmed highly, highly efficiently by someone who knows what they're doing and isn't clouded by doing things solely the x86 way.

Oh, and modern CPUs like the Core Duo emulate x86 macros down to more a more RISC-like central set. This is how Intel managed to make the jump from the hot, high-power P4's to relatively cooler and lower power Dual Core chips.

Reply Parent Score: 4

RE[3]: ?? instruction set ??
by rayiner on Mon 20th Aug 2007 21:00 in reply to "RE[2]: ?? instruction set ??"
rayiner Member since:

The Core 2 is actually less RISC-y internally than the P4. The P4 is internally a pure u-op design. The Core 2 caries fused u-ops (eg: mem-op instructions) through much of the frontend of the core.

As for PPC, ARM, and MIPS, one of those three does not belong. MIPS is a great instruction set. PowerPC is poo.

Reply Parent Score: 6

RE[4]: ?? instruction set ??
by Kroc on Mon 20th Aug 2007 21:15 in reply to "RE[3]: ?? instruction set ??"
Kroc Member since:

My bad then, but there are a number of variants of ARM, so it can be tight in some instances where even simple op-codes are un-available. However the Commodore style design, and the neat conditional prefixes make it a somewhat creative processor.

Reply Parent Score: 2

RE[5]: ?? instruction set ??
by rayiner on Mon 20th Aug 2007 21:40 in reply to "RE[3]: ?? instruction set ??"
rayiner Member since:

Oh, ARM is fine. It's PPC that doesn't belong. I just don't like the basic design (too many weird instructions, no separate 32-bit and 64-bit operations, etc).

MIPS is my favorite, but x86-64 comes in a close second. It's so much better than people give it credit for. It's actually quite orthogonal in its addressing and operand modes. You get 8-bit, 32-bit, and 64-bit registers, along with 8-bit, 32-bit, and 64-bit operations. You get 8-bit and 32-bit immediates and displacements, instead of the oddly-sized immediates and displacements you usually get in RISC. Instructions that write to fixed registers and two-operand instructions suck a bit, but you can deal with both quite easily in the register allocator.

Reply Parent Score: 3

RE[3]: ?? instruction set ??
by ecko on Tue 21st Aug 2007 13:10 in reply to "RE[2]: ?? instruction set ??"
ecko Member since:

Not even close. Intel has been converting from x86 to internal micro operations since the original Pentium more than 10 years ago.

PPC, ARM and RISC aren't in any way more efficient than x86. The ISA is just like and API and in no way reflects efficiency. A lot of issues with X86 are easily fixed by clever hardware design.

Yeah it's not as elegant as PPC or MIPS but it's also a lot older.

Reply Parent Score: 1

RE[4]: ?? instruction set ??
by helf on Tue 21st Aug 2007 17:06 in reply to "RE[3]: ?? instruction set ??"
helf Member since:

I thought the Pentium Pro was the first one to start doing that... Could be wrong.

Reply Parent Score: 3