Linked by Thom Holwerda on Tue 18th Sep 2007 19:52 UTC, submitted by Hendra
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Member since:
2007-09-19
If the three core chip is really a four core chip where one of the cores is not working, is it possible that the memory controller, HT bus, and L1, L2 cache that were used by the disabled core can be used to advantage by the remaining cores?