First theorized in the 1970's as the fourth basic circuit element, a practical memristor implementation has finally been discovered at HP Labs. If practical manufacturing can be scaled up, memristor technology could become the new standard for computer memory -- memory that combines the speed of DRAM, the persistence of Flash memory, and the bit density of hard drives. In addition, memristors can work as analog as well as digital devices, and hold promise as the basis for building neural networks
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Member since:2007-09-22
Member since:2005-11-09
Member since:2006-04-09
"50 GB L2 cache"
Led me to do a very rough thought experiment. A Core 2 processor at 65 nm process with 2 (might be 4) MB of cache is 143 square mm. Lets say cache is half of it, or 70 square mm.
If 50 GB ~= 50,000 MB, that's 2 MB * 25,000 to get 50 GB of cache. At a 65 nm process, that'd be 70 square mm * 25,000, or about 1,750,000 square mm.
That'd be a square of about 1,300 mm, or a square 1.3 meters per side. Each processor die would be about the size of a small table. If there's 64 of them, then that's a processor 10 meters per side. I guess if you arrange them in a stack you might end up with something like a small car.
I suppose that's only at 65 nm. Maybe with super gamma ray lithography or by pushing individual atoms around it'll get the size down to something that would be able for a person to carry easily.
I'm sure my math is off, but I'd hope my mistakes don't invalidate the orders of magnitude that MB -> GB includes.
"Not to mention size concerns" Indeed!
Member since:2005-09-14
Led me to do a very rough thought experiment. A Core 2 processor at 65 nm process with 2 (might be 4) MB of cache is 143 square mm. Lets say cache is half of it, or 70 square mm.
If 50 GB ~= 50,000 MB, that's 2 MB * 25,000 to get 50 GB of cache. At a 65 nm process, that'd be 70 square mm * 25,000, or about 1,750,000 square mm.
Bear in mind that current cache memory is SRAM, which because of its design takes up a lot more space than more conventional DRAM-type designs. We don't really know what memristor-based RAM will look like at this point, but based off some of the preliminary whitepapers it is capable of *very* high data density, so it should be capable of packing considerably more storage into the same space compared to SRAM.
Member since:2005-11-09
Member since:
2005-07-24
While it may be as fast as DRAM ( DDR? DDR2? ) there are still considerably faster types of memory I'd love to see fill the void of RAM. i.e. The L1/L2 cache memory which can give 20GB/s or better :-)
I would love to see the following setup:
(All memory persistent)
64 Core CPU ( w/ thread splitting and per-CPU rates )
Each core:
1GB 1PB/S L1, fully associative, versioning
50GB 500TB/S+ L2, fully associative, versioning
Global:
500GB 50TB/S+ L3, versioning, and flex-partitioned
RAM:
10TB 1TB/S+
Ultra High Capacity Storage:
18PB 500GB/S+, solid-state, w/ integrated interface-speed 10GB cache ( say, 1TB/s ).
The tiering is for cost :-) Not to mention size concerns :-)
This system would be very hard for Microsoft to slow down, though I am certain they would find a way.
But... I mean... Haiku would certainly be an instant-on OS even if no special work was done :-)
Windows Vista may take 100ms or so, being human-noticeable ( albeit tolerable ).
Heck, the CPU cores wouldn't even need to be that fast :-)
Ahh.. just imagine the games we could write!
It MIGHT even be able to run SETI so fast we end up waiting for the data to come from the telescopes every 10 seconds or so ( that would be sweeet ).
hmm... I seriously think I need to sleep more than four hours a day, but then I can't program for $@!# :-(