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As I understand it, the short story is that SRAM uses a bunch of transistors in a special configuration in order to stably hold its state, whereas DRAM uses a transistor and a capacitor. DRAM takes less space as a consequence but needs to be refreshed to recharge the capacitor in order to prevent from losing its state. The problem being that the more complex transistor design that SRAM uses takes up more space per bit than DRAM does, hence your 2MB cache on a die taking up half the die as opposed to the amount of space 2MB would take on your 1-2GB DIMMs. A hypothetical memristor-based RAM design could potentially be noticably smaller than even DRAM, and without needing the refresh cycle. We'll see what comes of it in practice, but the potential is there.






Member since:
2006-04-09
Thanks for the information. I vaguely recall reading some differences between DRAM and SRAM complexity years ago, but couldn't remember any details. I'm not a circuits person at all, just basic EE course in college.