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A majority of modern CPUs boot in less than a second. Much less in most cases.
I speak of embedded devices, of course, which outnumber every desktop CPU on the planet.
In many of these designs, if an error is detected, instead of handling the error the system reboots and is running again without anyone noticing it happened.
I don't think you understand how this works. This memristor is a *passive* circuit element. That means it does not have to have power running through it to retain it's flux. Current memory technology looses everything once it looses power, but this type of technology doesn't. So even if you turn your computer off, everything would still be in memory. There's no need to boot up when turning on the computer because everything is already loaded.
This has nothing to do with speed, it has to do with being able to set a bit value and retaining it without having to feed the circuit element power.
Actually I think I do understand the jist of it
I never said it was a volatile device needing continuous power, to keep the flux. I said that a flow of current or as the paper prefers to use the terms charge and voltage flux results in the moving of Oxygen atoms across an interface near a TiO layer, which in turn causes the resistance to change. If the current is removed, the resistance is still changed hence a bit state is stored. Presumably the Oxygen atoms can return if the current is restored in the reverse direction. I am guessing the charge and voltage applied would traverse a hysteresis sort of pattern not unlike the writing of old style magnetic core bits.
In order to make the device useful, would it not need an adjacent active switching device per bit to read the state? I fail to see how the technology will be useful without that, making it look pretty familiar. To be really practical, the memrister would need to be truly integrated into the transistor cell topology as with all DRAM, EPROM cells in which case it won't be any smaller or denser.
I will take this a lot more seriously when they have a real addressable large scale memory device with circuit diagrams in an ISSCC paper.
BTW even current memory may not be as volatile as you think.
Try researching Vt shifts. You may or may not know that after power down, SRAM and DRAM cells that are used to store constant data can give up that information to those with patience, money, tools. SRAM cells start off as balanced with almost the same Vt on both sides. Repeatedly reading the same data from an SRAM cell over many cycles and time will move the Vt of some devices slightly, making them asymmetric so that on power up they will tend to power up the same way. The author of PGP describes this in the notes as a way to extract keys from an unpowered computer. He toggles the key data while PGP runs.
Also DRAM cells also don't just lose data when powered off, they leak data away and that can take far longer than perhaps a few ms, it may take even several minutes for large parts of the array. Not quite non volatile or reliable enough to stretch out refresh cycles that long.
Also some vendors (like Motorola) have true non volatile DRAM using an extra magnetic component (see MRAM), but these are only available in small MByte sized chips. Many non volatile schemes have been proposed in the past, but only EEPROM and descendants remain.





Member since:
2005-07-08
Are you an EE or what?
I read the EET article too and another elsewhere and don't quite understand how we get to nirvana bit.
Seriously it sounds like all the talk of "this will really change my computer so it will always boot in a ms" is really just so much BS or just cluelessness. If you actually ran a small OS something like BeOS or even lighter, it actually could boot in a ms from a small Flash disk or MRAM. The old timers will remember that QNX once released a version with GUI and some small apps (including a modest browser IIRC) that really did fit on a floppy back in the day when every PC had one. Now 1.4MB. is small enough to fit in many caches today. Now bring that little beast up to date and it would be no big item to burn it into ROM and put the whole darn PC system on one chip.
The problem with our ever such sluggish computers isn't that the switching devices are still not yet fast enough and small enough, its that we have succumbed to pervasive bloat and absurd complexity at every level of the design both hardware and software. There is also the problem of the memory wall, the relative huge distance in performance between processor transistor speeds v DRAM or even disk rates both real disk and SSD. That only gets compounded by the oncoming thread wall.
Honestly the fastest OS-cpu out there is the one that does the least amount of work but still gets the same job done. I write this on a MiniMac OSX, the most sluggish PC I own but powered by the fastest processor I own. Seriously a 25yr old OS/PC running at a few MHz could boot from ROM in a sec, give it 1000x the cpu, and that would be 1ms boot time, there you go. Now somebody is going to point out it wouldn't do the same thing as todays wunderkind, I suppose it wouldn't.
rant mode off