Linked by Thom Holwerda on Thu 15th Sep 2005 12:20 UTC
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Member since:
2005-07-06
The article is a little misleading. The L2 cache was off-chip in the US-IV, but there was 8M/core (16M/socket). The new chip will have on-chip 2M L2 cache, as 32M off-chip.
Sun has also shrunk the die from 130nm to 90nm, which is what has allowed them to add the on-chip cache.