Linked by Thom Holwerda on Thu 29th Jan 2009 12:11 UTC
3D News, GL, DirectX Currently, NVIDIA is really missing out on the netbook market, which is dominated by all-Intel platform designs. NVIDIA has finally woken up to this reality, and the outspoken cofounder, president, and CEO of NVIDIA, Jen-Hsun Huang, has launched an all-out campaign to promote his company's Ion platform - and he isn't shy of flinging some poo to Intel and netbooks in general.
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Mage66
Member since:
2005-07-11

The Atom is already multi-core, netbooks use the single core version. The desktop Atom implementations use the dual core version.

Reply Parent Score: 1

bnolsen Member since:
2006-01-06

Apparently atom doesn't scale. What hurts x86 massively multi core is the comparatively "vast" amount of silicon required just for the x86 decoder. That's why intel went back to hyper threading. They can get more (inefficient) execution units while not having to replicate yet another x86 decoder.

The arm guys should get off their butts since the arm instruction set is far superior for low power small die truly multi core operation.

Likely nvidia's only way to get back in the game short term is to find a way toteam up with freescale and put together something with a cortex a8. The other arm core nvidia is supporting can't play in the netbook arena.

Reply Parent Score: 3

timofonic Member since:
2006-01-26

The arm guys should get off their butts since the arm instruction set is far superior for low power small die truly multi core operation.


Please look at your back first, because Cortex-A9 platform is multicore ;)

Reply Parent Score: 2

_txf_ Member since:
2008-03-17

well nvidia already have the tegra SoC, which I believe has an arm 11 core.

Reply Parent Score: 2

christian Member since:
2005-07-06

Apparently atom doesn't scale. What hurts x86 massively multi core is the comparatively "vast" amount of silicon required just for the x86 decoder. That's why intel went back to hyper threading. They can get more (inefficient) execution units while not having to replicate yet another x86 decoder.


There is nothing inherently inefficient with hyper-threading. It allows you to have relatively simple pipelines, and avoid pipeline bubbles by having multiple execution streams. Sounds like a great idea to me, and allows you to ramp up execution units and still use them relatively efficiently.

I'd rather have a HT core with 4 execution units than 2 non-HT core with 2 execution units each.

While avoiding duplication of decoder units is good argument for HT in x86, HT also works very well for RISC instruction sets as well, as it is the pipeline bubbles that HT effectively removes.

SPARC T1 & T2 is a good demonstration of HT with simple pipelines.

Reply Parent Score: 2