Linked by Thom Holwerda on Tue 1st Jun 2010 21:33 UTC
Intel "In an announcement at the International Supercomputing Conference, Intel provided further details on the many-core chip that it hinted at earlier in the month. The first product based on the new design will be codenamed Knight's Corner, and will debut at 22nm with around 50 x86 cores on the same die. Developer kits, which include a prototype of the design called Knight's Ferry, have been shipping to select partners for a while now, and will ship more broadly in the second half of the year. When Intel moves to 22nm in 2011, Knight's Corner will make its official debut."
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Comment by cb88
by cb88 on Wed 2nd Jun 2010 00:14 UTC
cb88
Member since:
2009-04-23

Would it have been any better had they named it Knight's Fury? No of course not but it really would have been a better name. It would have made more sense with Knight's Ferry being the developer version.

All I'm not impressed with intel so far their designs are little more than *take small cores and network together* which isn't the best approach for supercomputing IMO cloud computeing perhaps but not supercomputing.

Reply Score: 1

RE: Comment by cb88
by kaiwai on Wed 2nd Jun 2010 00:44 in reply to "Comment by cb88"
kaiwai Member since:
2005-07-06

Super computers don't actually require complicated CPU designs given that the instructions are fixed; all the CPU that is required to do is suck in the information, crunch it and spit out the other side. When you use a super computer for number crunching you're pushing in a sequence of equations and pumping out a result the other end so you can get away with stripping off branch prediction and so forth because all you're really interested in is raw power.

Have a simple CPU design, chain together those many cores, parallelise the code to buggery, a heck load of bandwidth and a clock speed going gang busters and you'll be all set to party.

Edited 2010-06-02 00:45 UTC

Reply Parent Score: 2

RE[2]: Comment by cb88
by drahca on Wed 2nd Jun 2010 11:36 in reply to "RE: Comment by cb88"
drahca Member since:
2006-02-23

Super computers don't actually require complicated CPU designs given that the instructions are fixed; all the CPU that is required to do is suck in the information, crunch it and spit out the other side.


Instructions are always fixed, it's called an ISA. And what you are describing seems to be some kind of stream processor. Most super computers need to be good in several tasks, with algorithms which can be parallelized successfully to varying degrees. Of course even if you parallelise it to bits there is always Amdahl's law.

When you use a super computer for number crunching you're pushing in a sequence of equations and pumping out a result the other end so you can get away with stripping off branch prediction and so forth because all you're really interested in is raw power.


You can only get away with stripping off branch prediction (and I presume other niceties such as Out Of Order Execution) if you have a well behaved algorithm, which you almost never have in reality. Of course some (parts of) algorithms run well on GPUs, which is what you seem to be describing here.

Have a simple CPU design, chain together those many cores, parallelise the code to buggery, a heck load of bandwidth and a clock speed going gang busters and you'll be all set to party.


Again, this only works for some algorithms. Communication between processors does not scale that well for most workloads. So you'd rather want fewer high performance cores, than more low performance cores. Scaling is not very important if your total performance still sucks.

If you don't believe me, check out the super computer top 500. Almost all systems use Xeons or Opterons.

What Intel is building here is interesting. Larrabee was supposed to be a many core x86 processor with massive vector units. The memory system was cache coherent using a massive ring bus. There were serious doubts as to if it would scale very well even for embarrassingly parallel workloads. This MIC might look more like the other project Intel had, in which there was no cache coherency but all chips were connected by a switched network and one had to use explicit message passing between threads in software, almost like a cluster on a chip.

Reply Parent Score: 2

RE: Comment by cb88
by ssokolow on Wed 2nd Jun 2010 00:44 in reply to "Comment by cb88"
ssokolow Member since:
2010-01-21

I saw an Intel video about these experimental many-core chip designs and cloud computing was specifically intended to be the target. Their whole goal is to explore ways to further improve space- and power-efficiency in cloud computing datacenters. (eg. by having 50 cores that consume as much as a single high-end CPU and can be throttled back to a 10th of that at off-peak times)

Reply Parent Score: 1