Linked by David Adams on Wed 4th Aug 2010 18:28 UTC, submitted by estherschindler
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Member since:
2009-05-12
They are talking about the processor pipeline. On a very high level, in RISC machines lets say each operation takes five cycles to complete. However one part of the cycle needs something from memory, in this case the operation cannot continue because it does not have any data. This causes a delay in the execution of the instruction. This is a level below the operating systems thread scheduler, as its the actual cpu(s) making choices on what operations are to be done.