Linked by Thom Holwerda on Thu 26th Aug 2010 23:24 UTC
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RE[5]: Are they still stuck in GHz race?
by tylerdurden on Sat 28th Aug 2010 18:10
in reply to "RE[4]: Are they still stuck in GHz race?"
Why would I need to read a 3rd party article, by a non-technical writer, when I was getting the specs directly from IBM?
Do you guys even comprehend the impossibility of a single chip at that 45nm process with those cache sizes?
See the specs from IBM directly, or if you need a 3rd party check wikipedia:
http://en.wikipedia.org/wiki/IBM_z196_(microprocessor)
A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.
RE[6]: Are they still stuck in GHz race?
by gilboa on Sun 29th Aug 2010 08:00
in reply to "RE[5]: Are they still stuck in GHz race?"
A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.
Actually, the biggest issue with large L1 is not flush-on-context switch.
The bigger the cache the bigger the index tables (assuming that they are not using direct mapped cache), which in turn, increases the latency.
As a result, L1 caches tend to small and extremely fast, with bigger and slower down the pipeline until you reach the main relatively slow main memory.
- Gilboa
RE[6]: Are they still stuck in GHz race?
by JAlexoid on Sun 29th Aug 2010 23:40
in reply to "RE[5]: Are they still stuck in GHz race?"
Why would I need to read a 3rd party article, by a non-technical writer, when I was getting the specs directly from IBM?
Do you guys even comprehend the impossibility of a single chip at that 45nm process with those cache sizes?
See the specs from IBM directly, or if you need a 3rd party check wikipedia:
http://en.wikipedia.org/wiki/IBM_z196_(microprocessor)
A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.
Do you guys even comprehend the impossibility of a single chip at that 45nm process with those cache sizes?
See the specs from IBM directly, or if you need a 3rd party check wikipedia:
http://en.wikipedia.org/wiki/IBM_z196_(microprocessor)
A 16 MB of L1 would be idiotic, since it could actually make things like context switches very costly with so much local data to flush in/out.
First of all, remember that Mainframes are designed to push I/O ops at unparalleled speeds. Their main focus forever was I/O performance, not processing speeds. That is why mainframe processors are not used in their super-computers, they are just not designed for raw calculations. Add to that, these machines are bundled with with some fast storage units - and you get ultra low wait times for data.
I've actually seen how these machines perform, Oracle RAC isn't a contender when comparing the I/O heavy DB operation performance these machines can achieve with DB2.





Member since:
2005-07-06
Look at the linked Yahoo News article: http://news.yahoo.com/s/zd/20100824/tc_zd/253938