Linked by Thom Holwerda on Thu 9th Sep 2010 13:00 UTC
Hardware, Embedded Systems So, we have Intel and AMD. These guys are doing pretty well in laptops, servers, and of course desktops, but when it comes to mobile devices, they've so far been unable to adapt the x86 architecture to the stricter requirements that come with those devices. ARM, on the other hand, pretty much owns this market at this point. And you know what? It's time for Intel and AMD to get worried - really worried. ARM has just announced its Cortex-A15 MPCore chips - which will reach 2.5Ghz in quad-core configurations.
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ARM isn't going for low power here
by theosib on Thu 9th Sep 2010 14:42 UTC
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We're on the cusp of the many-core era. Putting aside supercomputers from the likes of Cray, a consumer, right now, can easily build a machine with two Magny-Cours, for a total of 24 execution cores in one box. And Intel has unveiled some interesting prototypes like their 80-core CMP and Larrabee.

Right now, we're still interested in single-thread performance, and adapting to multicore is difficult. But looking forward, we expect multicore performance to dominate. Assuming you have unlimited parallelism available, it's best to cram as many simple cores onto a die as possible for a given power budget.

So rather than a handful of fast x86 cores, we're going to see CPU packages with dozens or hundreds of simple cores like what ARM puts out. Instead of 4 Intel processors in 130 watts, you get 130 1-watt ARM processors in the same space and power budget.

This isn't about conserving power. It's maximizing compute per watt.

ARM processors aren't really just low-power. They're low AVERAGE power. At 32nm leakage (idle) power actually dominates. ARM's strength is and has always been having exceptional computational efficiency to blast through work quickly and then SHUT OFF. With the Cortex A9, the granularity has been refined from while-core down to individual computational functional units in a core. ARM instructions first require less power to decode and execute, because it's a RISC processor and the decode is basically nil, and more computationally efficient because things like predication are built into every instruction.

For a frame of reference, there was an IBM supercomputer designed a few years ago that was made up of, basically, G4 processors. The thing was, the interconnects between processors were the dominant efficiency bottleneck. To pack more compute power into the same space, they underclocked the processors to 800MHz. The cores were more power efficient, so for they could build a bigger supercomputer, and get more compute power for the same power budget.

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