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Technically, the "Reduced" in RISC does not mean "fewer number of instructions" rather than a reduction in the complexity of the instructions in the ISA. It helps to think that the opposite of RISC is CISC, the C is not for "lots of instruction" instructions but for "Complex."
Ironically, even most mainstream RISC had to further reduce the complexity of their instructions by adding "crack" stages to further distill some RISC insts into even more simpler micro-ops when they introduced out-of-order scheduling.
Therefore, by the last decade there was little difference between the high end X86 OOO parts and the high performance RISC processors. Which is why RISC went the way of the dodo in certain markets, because it had zero value proposition over the competing x86 parts which could enjoy mass production and thus cheaper prices.
Member since:
2005-06-29
And mainstream RISC architectures added more instructions (Altivec, etc). Extremes are almost never useful.