Linked by nfeske on Thu 24th Feb 2011 23:27 UTC
OSNews, Generic OSes The just released version 11.02 of the Genode OS Framework pushes its platform support to 8 different kernels. Genode allows the construction of specialized operating systems by combining one of those kernels with a steadily growing number of ready-to-use components. The new platform additions are the support for Fiasco.OC, which is a modern capability-based microkernel, the upgrade to the NOVA hypervisor 0.3, and a custom kernel implementation specifically targeted to softcore CPUs as employed in FPGA-based SoCs. Functionality-wise, Genode 11.02 features the first parts of a new execution environment for running command-line-based GNU software natively on Genode.
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RE: Scalability
by Elv13 on Sat 26th Feb 2011 05:13 UTC in reply to "Scalability "
Elv13
Member since:
2006-06-12

Well, as I see it, it is the other way around, at least for the new features in this release. It look like on how little can you scale it down. Running a modern OS on a FPGA is nice, it may be the future after all. Sure, CPUs are good, but FPGA are more flexible. Think of a cache like mechanism for actual code. A pool of soft wired logic gates in a big, fat and powerful CPU. You can use them asynchronously, executing heavy functions that require hundreds of cycles in a single one or poping physical threads on the fly to run light weight but real time process completely cut off from the main CPU while having access to its memory in true DMA mode. It could speed up application by hundreds of times given that a FPGA is able to process certain information faster than a CPU (when well used) while it is not even 1% of the size in term of transistors.

I would love to have a good platform for that, and this kind of OS might just be a perfect fit.

Reply Parent Score: 2

RE[2]: Scalability
by Jondice on Sat 26th Feb 2011 05:34 in reply to "RE: Scalability "
Jondice Member since:
2006-09-20

I take your point, and it will be nice if more mainboards become available having an FPGA socket in addition to all of their processor sockets. I think that would begin to increase the prevalence of FPGA-optimized code, which would be fantastic, especially if this was done in terms of existing UNIX libraries simply by replacing the algorithms done in C with something done in verilog or vhdl, so that it would be transparent to the user.

It isn't the first time I'd wished I had an FPGA either, and it looks like my (core) algorithm-of-need has already been implemented for one:
http://imperial.academia.edu/SamuelBayliss/Papers/229087/An_FPGA_Im...


My question wasn't really directed at this release, but it is a potentially practical question (for me).

Reply Parent Score: 2

RE[3]: Scalability
by Elv13 on Sat 26th Feb 2011 07:24 in reply to "RE[2]: Scalability "
Elv13 Member since:
2006-06-12

I wonder if something like Microsoft CLR or LLVM runtime compilation could detect functions that can be implemented in pure logic (1 cycle per function) or logic+some latches (some cycle, but most merged together) and let the runtime compilator to produce the most "valuable" set of logic function for a given time or context. Let face it, it would not be like a CPU, unless it is done wrong, you can know at compile time how much gates you would be available at a given time and a given motherboard, as they would grow in transistor count while normal CPU grow in instruction set.

Reply Parent Score: 2