Linked by nfeske on Thu 24th Feb 2011 23:27 UTC
OSNews, Generic OSes The just released version 11.02 of the Genode OS Framework pushes its platform support to 8 different kernels. Genode allows the construction of specialized operating systems by combining one of those kernels with a steadily growing number of ready-to-use components. The new platform additions are the support for Fiasco.OC, which is a modern capability-based microkernel, the upgrade to the NOVA hypervisor 0.3, and a custom kernel implementation specifically targeted to softcore CPUs as employed in FPGA-based SoCs. Functionality-wise, Genode 11.02 features the first parts of a new execution environment for running command-line-based GNU software natively on Genode.
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RE[2]: Scalability
by Jondice on Sat 26th Feb 2011 05:34 UTC in reply to "RE: Scalability "
Jondice
Member since:
2006-09-20

I take your point, and it will be nice if more mainboards become available having an FPGA socket in addition to all of their processor sockets. I think that would begin to increase the prevalence of FPGA-optimized code, which would be fantastic, especially if this was done in terms of existing UNIX libraries simply by replacing the algorithms done in C with something done in verilog or vhdl, so that it would be transparent to the user.

It isn't the first time I'd wished I had an FPGA either, and it looks like my (core) algorithm-of-need has already been implemented for one:
http://imperial.academia.edu/SamuelBayliss/Papers/229087/An_FPGA_Im...


My question wasn't really directed at this release, but it is a potentially practical question (for me).

Reply Parent Score: 2

RE[3]: Scalability
by Elv13 on Sat 26th Feb 2011 07:24 in reply to "RE[2]: Scalability "
Elv13 Member since:
2006-06-12

I wonder if something like Microsoft CLR or LLVM runtime compilation could detect functions that can be implemented in pure logic (1 cycle per function) or logic+some latches (some cycle, but most merged together) and let the runtime compilator to produce the most "valuable" set of logic function for a given time or context. Let face it, it would not be like a CPU, unless it is done wrong, you can know at compile time how much gates you would be available at a given time and a given motherboard, as they would grow in transistor count while normal CPU grow in instruction set.

Reply Parent Score: 2