OSNews Asks: Interrupt Mechanisms on non-x86 Architectures
Linked by Hadrien Grasland on Sun 27th Feb 2011 12:06 UTC
Hardware, Embedded Systems This is a situation where I need the help of you OSnews readers who are experienced with low-level development on ARM, SPARC, PowerPC, MIPS, and other hardware architectures we have on computers nowadays. The issue is that I'm currently designing the part of my hobby kernel which takes care of interrupts. Although I mostly work on x86 at the moment, I'd like to keep this code portable to other hardware architectures in the future. To do that, I have to know how interrupt handling works on as much HW architectures as possible.
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In my limited experience
by rexstuff on Mon 28th Feb 2011 07:59 UTC
rexstuff
Member since:
2007-04-06

In my somewhat limited experience, the basic idea of interrupt handling is pretty universal across platforms. An interrupt comes in, consults the vector table and jumps to appropriate address/service routine. Variation comes into play wrt how the table is accessed, how and what sort of masking can take place, etc. I don't anticipate it would be too difficult to abstract that away.

You'd basically hook a couple of function call like:

void program_isv(int interrupt_number, &service_routine() );
int mask_interrupts(int interrupt_mask);

etc, making them implementation specific. But while I've worked on embedded systems, I've never written my own kernel (from scratch), so take that with a significant grain of salt.

I think some of our earlier commenters are too kind on the 68k line. It was a good architecture, make no mistake, but among other things, the instruction set was too bloated. It was partly because of CISC processors like the 68k that we saw such a movement toward much more RISC processors like ARM, culminating in excessively small ISs like the ridiculous PIC. But anyway. Such are my opinions.

Reply Score: 2

RE: In my limited experience
by Neolander on Mon 28th Feb 2011 08:22 in reply to "In my limited experience"
Neolander Member since:
2010-03-08

So that matches my model in the article ;)

OTOH, looking at all these manuals I've started to collect, there could be a notion which I might like to keep instead of abstracting it out, that of interrupt priority.

As said earlier, in the VAX family, high-priority interrupts could preempt the interrupt handler of lower-priority interrupts. It also seems to work this way on the MIPS architecture.

Even without going this far, many other architectures seem to have some mechanism for prioritizing some interrupts above others. ARM chips have their IRQ and FIQ pins where FIQ interrupts are prioritized over IRQ interrupts in case of simultaneous events, x86 takes the lowest interrupt vector in such cases if I remember well, and so on.

Maybe this priority information could be useful later (one could imagine e.g. starting higher-priority threads to handle higher-priority interrupts). I don't think I should abstract it out right now.

Edited 2011-02-28 08:24 UTC

Reply Parent Score: 1

RE: In my limited experience
by renox on Mon 28th Feb 2011 09:32 in reply to "In my limited experience"
renox Member since:
2005-07-06

I think some of our earlier commenters are too kind on the 68k line. It was a good architecture, make no mistake, but among other things, the instruction set was too bloated.


Well bloat is a relative thing: the 68k ISA is quite lean compared to the VAX ISA ;-)

And amusingly most RISC now have a variable length instruction set variant: ARM Thumb, MIPS, etc.

Reply Parent Score: 2