Linked by Hadrien Grasland on Thu 19th May 2011 21:31 UTC
Hardware, Embedded Systems Having read the feedback resulting from my previous post on interrupts (itself resulting from an earlier OSnews Asks item on the subject), I've had a look at the way interrupts work on PowerPC v2.02, SPARC v9, Alpha and IA-64 (Itanium), and contribute this back to anyone who's interested (or willing to report any blatant flaw found in my posts). I've also tried to rework a bit my interrupt handling model to make it significantly clearer and have it look more like a design doc and less like a code draft.
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PowerPC v2 ?
by DeepThought on Fri 20th May 2011 07:34 UTC
DeepThought
Member since:
2010-07-17

I am not sure what you mean by PowerPC v2. But there is more than one interrupt handling theme on PowerPC.
Some (like the e200 cores) use hardware vectoring but can be switched back to SW mode.
The e300/e500 cores do only SW interrupt handling.

IMHO HW vectoring pays off only if one does use not any kind of (RT)OS.

Anyway, besides the peripheral interrupts, there are always the exceptions.

Ah, and there are sometimes two vectors for peripheral interrupts.

Reply Score: 1

RE: PowerPC v2 ?
by Neolander on Fri 20th May 2011 11:43 in reply to "PowerPC v2 ?"
Neolander Member since:
2010-03-08

I'll check once I'm at home and have my stack of manuals at hand, but I think there was something like "PowerPC v2.1" written on the first page of the manual, so I assumed that this architecture had, like ARM, seen several revisions.

Edited 2011-05-20 11:47 UTC

Reply Parent Score: 1

RE[2]: PowerPC v2 ?
by DeepThought on Fri 20th May 2011 12:50 in reply to "RE: PowerPC v2 ?"
DeepThought Member since:
2010-07-17

Actually the last public Power (now w/o PC) ISA is 2.06.
But it does not describe interrupt handling.
Much of it depends on the implementation. Means IBM does it different from Freescale. And Freescale even has different interrupt handling depending on the core.

Reply Parent Score: 1